Documentation for project sigasi-cli-docgen-demo

Module counter

This design unit is implemented in step_1_dut_core.sv

Description

TODO "Validation: parameters" For the next steps in this tutorial, you need a Sigasi Studio license. If you don't have one already, request your trial license at https://www.sigasi.com/try-buy (you can Ctrl+Click here too)

Parameters and Ports

Parameters

Name	Type	Default Value	Description
`WIDTH`		`16`

Ports

Name	Direction	Type
`clk`	`input`	`wire logic`
`rst`	`input`	`wire logic`
`start`	`input`	`wire logic`
`enable`	`input`	`wire logic`
`endvalue`	`input`	`wire logic [(WIDTH-1):0]`
`count`	`output`	`wire logic [(WIDTH-1):0]`
`near_end`	`output`	`logic`
`on_edge`	`output`	`logic`

Always Blocks

unnamed : always
- And 1 more

Block Diagram

Module dut_core

This design unit is implemented in step_1_dut_core.sv

Description

TODO "Correct syntax error" Sigasi Studio puts error markers in the left hand side margin when a syntax error is found. Sigasi Studio marks errors while you are typing. The earlier errors are found, the easier they are to fix.

Parameters and Ports

Ports

Name	Direction	Type
`pixel_out`	`output`	`logic [7:0]`
`pixel_pp`	`input`	`wire logic [7:0]`
`pixel_p0`	`input`	`wire logic [7:0]`
`pixel_pm`	`input`	`wire logic [7:0]`
`pixel_0p`	`input`	`wire logic [7:0]`
`pixel_0m`	`input`	`wire logic [7:0]`
`pixel_mp`	`input`	`wire logic [7:0]`
`pixel_m0`	`input`	`wire logic [7:0]`
`pixel_mm`	`input`	`wire logic [7:0]`
`on_edge`	`input`	`wire logic`
`clock`	`input`	`wire logic`
`reset`	`input`	`wire logic`

Always Blocks

unnamed : always
- TODO "Autocompletion" On the blank line below, type the first letters of always and then Ctrl+Space. Select Insert an always block with posedge clk (double-click, or use arrow up/down and press enter). An always block is generated and clk is selected. Type cl (replacing clk) and press Ctrl+Space again to auto-select clock which is our clock signal.

unnamed : always_ff

Block Diagram

Module dut_engine

This design unit is implemented in step_5_dut_engine.sv

Parameters and Ports

Ports

Name	Direction	Type
`clk`	`input`	`wire logic`
`rst`	`input`	`wire logic`
`start`	`input`	`wire logic`
`extra_at_start`	`input`	`wire logic`
`start_x`	`output`	`logic`
`enable_x`	`output`	`logic`
`near_end_x`	`input`	`wire logic`
`start_y`	`output`	`logic`
`enable_y`	`output`	`logic`
`near_end_y`	`input`	`wire logic`
`pixel_valid`	`output`	`logic`
`idle`	`output`	`logic`

Always Blocks

unnamed : always

State Machine

Source	Target	Condition	Comment
calculate	finish_row_1	`near_end_y == 1'b1 && near_end_x == 1'b1`	main calculation done
finish_row_1	finish_row_2	`extra_at_start == 1'b0 near_end_x == 1'b1`	extra line at end
finish_row_1	waiting	`near_end_x == 1'b1`	all done
finish_row_2	waiting	`near_end_x == 1'b1`	edit the label
startup_row_1	calculate	`near_end_x == 1'b1`
startup_row_1	startup_row_2	`extra_at_start == 1'b1 near_end_x == 1'b1`	extra line at start
startup_row_2	calculate	`near_end_x == 1'b1`
waiting	startup_row_1	`start == 1'b1`	received start

Block Diagram

Module dut_top

This design unit is implemented in step_2_dut_top.sv

This file depends on: step_1_dut_core.sv, step_5_dut_engine.sv, step_3_pixelbuffer.sv

Parameters and Ports

Ports

Name	Direction	Type	Description
`clk`	`input`	`wire logic`	core clock
`rst`	`input`	`wire logic`	system reset
`start`	`input`	`wire logic`	start DUT (pulse)
`size_x`	`input`	`wire logic [11:0]`	image width
`size_y`	`input`	`wire logic [11:0]`	image height
`pixel_in`	`input`	`wire logic [7:0]`	pixel in (streaming input)
`pixel_out`	`output`	`wire logic [7:0]`	pixel out (streaming output)
`pixel_valid`	`output`	`wire logic`	indicates that the output pixel is valid

Instantiations

counter_x_instance : counter

Congratulations, you've made it to the second part of the tutorial. In this part, we'll focus on Navigating the code and using the different Views of Sigasi Studio.

counter_y_instance : counter

TODO "Project Explorer" and "Library mapping" In the window to the left of the editor, navigate to the Project Explorer tab.

dut_engine_instance : dut_engine

TODO "Autocomplete instance" Add an instance of component dut_engine. On an empty line, enter the first characters of dut_engine. Press Ctrl+Space and double-click dut_engine - Instantiate design unit to create the instantiation. Press Tab multiple times to go through the instance connections, and Enter to return to normal editing mode. Finally, press Ctrl+S to save the file.

dut_core_instance : dut_core

TODO "Validation: instances" The instance of dut_core below contains a mistake, which is indicated by two problem markers. Place the mouse pointer over the problem marker or underlined code to see a pop-up with an explanation of the problem. One port name was misspelled, which is seen as a missing port connection (pixel_mm) and a duplicate one (pixel_m0).

pixelbuffer_instance : pixelbuffer

TODO "Open declaration" On the line below, select pixelbuffer and press F3 to navigate to the declaration of module pixelbuffer.

Block Diagram

Module image_testbench

This design unit is implemented in step_6_image_testbench.sv

This file depends on: drive_rst_start.vhd, step_2_dut_top.sv

Description

Standardized header of my.compa.ny

Top-level testbench of the Imaginary Project

Author: Sigasi Team

Instantiations

drive_rst_start_instance : drive_rst_start

Driver block for reset and start indication

dut_top_instance : dut_top

DUT instance

Initial Blocks

unnamed : initial
- Initialize the source image

Always Blocks

unnamed : always
- Clock generator

unnamed : always
- Feed data into the DUT

Block Diagram

Module pixel_testbench

This design unit is implemented in step_4_pixel_testbench.sv

This file depends on: step_2_dut_top.sv

Description

Module pixel_testbench implements a first testbench for the design under test.

Instantiations

inst_dut_top_instance : dut_top

TODO "Naming conventions" Sigasi Studio can help to enforce naming conventions of various design items, e.g. to enforce that instance names start with inst_.

Always Blocks

unnamed : always
- Feed data into the DUT
  State Machine
  Source Target Condition
  IDLE RUNNING start
  READY IDLE
  RUNNING READY

Source	Target	Condition
IDLE	RUNNING	`start`
READY	IDLE
RUNNING	READY

unnamed : always
- Clock generator

Block Diagram

Module pixelbuffer

This design unit is implemented in step_3_pixelbuffer.sv

This file depends on: ram.sv

Description

Module pixelbuffer implements a buffer to contain 2 pixel rows + 3 pixels of the image. Pixels arrive into the buffer in a streaming mode. A 3x3 pixel window (without the central pixel) is offered at the output.

This is a behavioral implementation, not suitable for synthesis.

Parameters and Ports

Ports

Name	Direction	Type	Description
`clk`	`input`	`wire logic`	core clock and synchronous reset
`rst`	`input`	`wire logic`	core clock and synchronous reset
`size_x`	`input`	`wire logic [11:0]`	image width
`pixel_in`	`input`	`wire logic [(24-1):0]`	input pixel
`pixel_in_valid`	`input`	`wire logic`	incoming pixel is valid
`pixel_pp`	`output`	`logic [(24-1):0]`	3x3 pixel window: upper right
`pixel_p0`	`output`	`logic [(24-1):0]`	3x3 pixel window: middle right
`pixel_pm`	`output`	`logic [(24-1):0]`	3x3 pixel window: bottom right
`pixel_0p`	`output`	`logic [(24-1):0]`	3x3 pixel window: upper middle
`pixel_0m`	`output`	`logic [(24-1):0]`	3x3 pixel window: lower middle
`pixel_mp`	`output`	`logic [(24-1):0]`	3x3 pixel window: upper left
`pixel_m0`	`output`	`logic [(24-1):0]`	3x3 pixel window: middle left
`pixel_mm`	`output`	`logic [(24-1):0]`	3x3 pixel window: bottom left

Instantiations

ram_instance : ram

This is a (so far) unused instantiation of a RAM module.
Feel free to edit here and observe the documentation view.
- Note that markdown
- is available to format your text!

Always Blocks

unnamed : always
- And 1 more

Block Diagram

Module ram

This design unit is implemented in ram.sv

Description

A naive RAM module without an impementation

Parameters and Ports

Parameters

Name	Type	Default Value	Description
`addrwidth`		`8`
`datawidth`		`8`

Ports

Name	Direction	Type	Description
`clk`	`input`	`wire logic`	clock
`rst`	`input`	`wire logic`	reset
`address`	`input`	`wire logic [addrwidth-1:0]`	address
`ren`	`input`	`wire logic`	read enable
`wen`	`input`	`wire logic`	write enable
`data_in`	`input`	`wire logic [datawidth-1:0]`	data in
`data_out`	`output`	`logic [(datawidth-1):0]`	data out

Documentation for project sigasi-cli-docgen-demo

Table of Contents

Project files overview

Design Units

Module counter

Description

Parameters and Ports

Parameters

Ports

Always Blocks

Block Diagram

Module dut​_core

Description

Parameters and Ports

Ports

Always Blocks

Block Diagram

Module dut​_engine

Parameters and Ports

Ports

Always Blocks

State Machine

Block Diagram

Module dut​_top

Parameters and Ports

Ports

Instantiations

Block Diagram

Module image​_testbench

Description

Instantiations

Initial Blocks

Always Blocks

Block Diagram

Module pixel​_testbench

Description

Instantiations

Always Blocks

State Machine

Block Diagram

Module pixelbuffer

Description

Parameters and Ports

Ports

Instantiations

Always Blocks

Block Diagram

Module ram

Description

Parameters and Ports

Parameters

Ports

Block Diagram

Entity work.drive​_rst​_start

Architectures

Generics and Ports

Ports

Architecture work.drive​_rst​_start(RTL)

Processes

Block Diagram

Module dut_core

Module dut_engine

Module dut_top

Module image_testbench

Module pixel_testbench

Entity work.drive_rst_start

Architecture work.drive_rst_start(RTL)