Generated by Sigasi 5.5.0.202312210927
Revision 2023-12-21
Project veresta-docgen-demo has 10 design units.
This design unit is implemented in step_1_dut_core.sv
| Name | Type | Default Value | Description |
|---|---|---|---|
WIDTH | 16 |
| Name | Direction | Type | Description |
|---|---|---|---|
clk | in | wire logic | |
rst | in | wire logic | |
start | in | wire logic | |
enable | in | wire logic | |
endvalue | in | wire logic [(WIDTH-1):0] | |
count | out | wire logic [(WIDTH-1):0] | |
near_end | out | logic | |
on_edge | out | logic |
unnamed : alwaysAnd 1 more
This design unit is implemented in step_1_dut_core.sv
| Name | Direction | Type | Description |
|---|---|---|---|
pixel_out | out | logic [7:0] | |
pixel_pp | in | wire logic [7:0] | |
pixel_p0 | in | wire logic [7:0] | |
pixel_pm | in | wire logic [7:0] | |
pixel_0p | in | wire logic [7:0] | |
pixel_0m | in | wire logic [7:0] | |
pixel_mp | in | wire logic [7:0] | |
pixel_m0 | in | wire logic [7:0] | |
pixel_mm | in | wire logic [7:0] | |
on_edge | in | wire logic | |
clock | in | wire logic | |
reset | in | wire logic |
unnamed : alwaysTODO "Autocompletion"
On the blank line below, type the first letters of always and then Ctrl+Space.
Select Insert an always block with posedge clk (double-click, or use
arrow up/down and press enter). An always block is generated and clk is selected.
Type cl (replacing clk) and press Ctrl+Space again to auto-select clock
which is our clock signal.
unnamed : always_ffThis design unit is implemented in step_5_dut_engine.sv
| Name | Direction | Type | Description |
|---|---|---|---|
clk | in | wire logic | |
rst | in | wire logic | |
start | in | wire logic | |
extra_at_start | in | wire logic | |
start_x | out | logic | |
enable_x | out | logic | |
near_end_x | in | wire logic | |
start_y | out | logic | |
enable_y | out | logic | |
near_end_y | in | wire logic | |
pixel_valid | out | logic | |
idle | out | logic |
unnamed : alwaysThis design unit is implemented in step_2_dut_top.sv
This file depends on: step_1_dut_core.sv, step_5_dut_engine.sv, step_3_pixelbuffer.sv
| Name | Direction | Type | Description |
|---|---|---|---|
clk | in | wire logic | core clock |
rst | in | wire logic | system reset |
start | in | wire logic | start DUT (pulse) |
size_x | in | wire logic [11:0] | image width |
size_y | in | wire logic [11:0] | image height |
pixel_in | in | wire logic [7:0] | pixel in (streaming input) |
pixel_out | out | wire logic [7:0] | pixel out (streaming output) |
pixel_valid | out | wire logic | indicates that the output pixel is valid |
counter_x_instance : countercounter_y_instance : counterdut_engine_instance : dut_enginedut_core_instance : dut_corepixelbuffer_instance : pixelbufferThis design unit is implemented in step_6_image_testbench.sv
This file depends on: drive_rst_start.vhd, step_2_dut_top.sv
Standardized header of my.compa.ny
(c) 2020 MyCo Inc. All rites reversed.
Top-level testbench of the Imaginary Project
Author: Sigasi Team
drive_rst_start_instance : drive_rst_startDriver block for reset and start indication
dut_top_instance : dut_topDUT instance
unnamed : initialInitialize the source image
unnamed : alwaysClock generator
unnamed : alwaysFeed data into the DUT
This design unit is implemented in step_4_pixel_testbench.sv
This file depends on: step_2_dut_top.sv
inst_dut_top_instance : dut_topTODO "Naming conventions"
Sigasi Studio can help to enforce naming conventions of various design items,
e.g. to enforce that instance names start with inst_.
unnamed : alwaysFeed data into the DUT
unnamed : alwaysClock generator
This design unit is implemented in step_3_pixelbuffer.sv
This file depends on: ram.sv
Module pixelbuffer implements a buffer to contain 2 pixel rows + 3 pixels of the image. Pixels arrive into the buffer in a streaming mode. A 3x3 pixel window (without the central pixel) is offered at the output.
This is a behavioral implementation, not suitable for synthesis.
| Name | Direction | Type | Description |
|---|---|---|---|
clk | in | wire logic | core clock and synchronous reset |
rst | in | wire logic | core clock and synchronous reset |
size_x | in | wire logic [11:0] | image width |
pixel_in | in | wire logic [(24-1):0] | input pixel |
pixel_in_valid | in | wire logic | incoming pixel is valid |
pixel_pp | out | logic [(24-1):0] | 3x3 pixel window: upper right |
pixel_p0 | out | logic [(24-1):0] | 3x3 pixel window: middle right |
pixel_pm | out | logic [(24-1):0] | 3x3 pixel window: bottom right |
pixel_0p | out | logic [(24-1):0] | 3x3 pixel window: upper middle |
pixel_0m | out | logic [(24-1):0] | 3x3 pixel window: lower middle |
pixel_mp | out | logic [(24-1):0] | 3x3 pixel window: upper left |
pixel_m0 | out | logic [(24-1):0] | 3x3 pixel window: middle left |
pixel_mm | out | logic [(24-1):0] | 3x3 pixel window: bottom left |
unnamed : alwaysAnd 1 more
This design unit is implemented in ram.sv
A naive RAM module without an impementation
| Name | Type | Default Value | Description |
|---|---|---|---|
addrwidth | 8 | ||
datawidth | 8 |
| Name | Direction | Type | Description |
|---|---|---|---|
clk | in | wire logic | clock |
rst | in | wire logic | reset |
address | in | wire logic [addrwidth-1:0] | address |
ren | in | wire logic | read enable |
wen | in | wire logic | write enable |
data_in | in | wire logic [datawidth-1:0] | data in |
data_out | out | logic [(datawidth-1):0] | data out |
This design unit is implemented in drive_rst_start.vhd
| Name | Direction | Type | Description |
|---|---|---|---|
rst | out | std_logic | |
start | out | std_logic |
This design unit is implemented in drive_rst_start.vhd
This architecture implements entity work.drive_rst_start
proc_stim